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TMS320C5515
www.ti.com
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 2-18. GPIO Terminal Functions (continued)
SIGNAL
NAME
LCD_D[13]/
UART_CTS/
GP[29]/
I2S3_FS
LCD_D[14]/
UART_RXD/
GP[30]/
I2S3_RX
LCD_D[15]/
UART_TXD/
GP[31]/
I2S3_DX
NO.
P13
N13
P14
TYPE (1)
(2)
I/O/Z
I/O/Z
I/O/Z
OTHER (3)
IPD
DV DDIO
BH
IPD
DV DDIO
BH
IPD
DV DDIO
BH
(4)
DESCRIPTION
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For GPIO, it is general-purpose input/output pin 29 (GP[29]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For GPIO, it is general-purpose input/output pin 30 (GP[30]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For GPIO, it is general-purpose input/output pin 31 (GP[31]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
Copyright ? 2010–2013, Texas Instruments Incorporated
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